About Us
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Our mission
  • We keep tracking a broad area of academic research and technology development in Digital Testing.
  • We make emphasis over design for testability and embedded testing technologies.
  • Our mission is development of new tools and services in digital testing.
  • We are also active in the area of education and training.

Academic Background

Although Testonica Lab is a very young company, our team has a long history of strong academic research traditions. During over 30 years of experience in the field we have been active in:
  • defect study and defect modeling of CMOS circuits;
  • fault modeling and fault simulation;
  • circuit and system level modeling;
  • test generation: logic-level, high-level, and hierarchical ones;
  • fault and error diagnosis;
  • design for testability;
  • built-in self-test (BIST) and hybrid BIST;
  • Boundary Scan and interconnect testing;
  • at-speed, delay, and crosstalk testing;
  • low power testing;
  • SoC and NoC testing solutions;
  • etc.
Our expert group has a deep expertise in these research topics where it is continuously active producing more than 20 publications each year.