APRICOT verification framework was presented at the University Booth of the DATE 2009 Conference and Exhibition in Nice
On Thursday, April 23rd, visitors of DATE Conference and Exhibition held this year in Nice had a chance to see a new hardware verification framework APRICOT that was jointly developed by Testonica Lab and Tallinn University of Technology (TUT) in the frames of the ELIKO Technological Development Center project.
APRICOT is an acronym for Assertions checking (monitoring), formal PRoperty checkIng, verification COverage measurement and Test pattern generation. The novelty of APRICOT lays in application of the High-Level Decision Diagrams (HLDD) design representation model advantages for simulation-based and formal verification tasks (e.g. assertion checking and code coverage analysis). Using ApricotCAD one can convert VHDL design representation to HLDDs as well as assertions described in IEEE-1850 PSL to THLDD. Further, one can simulate the design with a predetermined or random stimuli, analyze the obtained structural coverage and check assertions.
The APRICOT verification framework is easy to use due to the variety of the available interfaces to the common design formats such as VHDL, SystemC, PSL and EDIF. Recently published experimental results show the advantages of HLDD-based verification tools compared to the tools from the major EDA/CAD vendors.