01.05.2009 - 07:00

Testonica signs a technology partnership agreement with GOEPEL electronic for extended JTAG/Boundary Scan

In April 2009, Testonica Lab and GOEPEL electronic GmbH signed an agreement that elevates the level of mutual cooperation of both partners towards technological development in the field of JTAG/Boundary Scan. In the frames of the new agreement Testonica Lab was incorporated into the global alliance program GATE™ (GOEPEL Associated Technical Experts) at the highest level as a Centre of Expertise (COE).

GOEPEL electronic GmbH, based in Jena, Germany, is a worldwide leading vendor of JTAG/Boundary Scan solutions compliant with IEEE1149.x. "Already during the last years, we’ve collaborated with Testonica as an application centre for our products, and were impressed by the excellent performance and competence of the team," says Frank Amm, Corporate GATE Program Manager at GOEPEL electronic. "In this respect, the recently arranged cooperation marks another step towards an even closer and more enduring collaboration of both companies, now including joint product development"

As the result of the new strategic development partnership we expect more exciting breakthroughs in technology and productivity to come soon due to achieving an unseen synergy through a combination of complementary competences and a new level of commitment of participating partners. Participation in the GATE™ program enables Testonica Lab to offer its unique services and technologies to GOEPEL customers as a part of complex turnkey solutions that have not been possible in the past.

Read complete press release.

29.04.2009 - 07:00

APRICOT verification framework was presented at the University Booth of the DATE 2009 Conference and Exhibition in Nice

On Thursday, April 23rd, visitors of DATE Conference and Exhibition held this year in Nice had a chance to see a new hardware verification framework APRICOT that was jointly developed by Testonica Lab and Tallinn University of Technology (TUT) in the frames of the ELIKO Technological Development Center project.

APRICOT is an acronym for Assertions checking (monitoring), formal PRoperty checkIng, verification COverage measurement and Test pattern generation. The novelty of APRICOT lays in application of the High-Level Decision Diagrams (HLDD) design representation model advantages for simulation-based and formal verification tasks (e.g. assertion checking and code coverage analysis). Using ApricotCAD one can convert VHDL design representation to HLDDs as well as assertions described in IEEE-1850 PSL to THLDD. Further, one can simulate the design with a predetermined or random stimuli, analyze the obtained structural coverage and check assertions.

The APRICOT verification framework is easy to use due to the variety of the available interfaces to the common design formats such as VHDL, SystemC, PSL and EDIF. Recently published experimental results show the advantages of HLDD-based verification tools compared to the tools from the major EDA/CAD vendors.

Visit the APRICOT website at TUT.

Download the APRICOT poster.

15.04.2009 - 07:00

Trainer 1149 1.1 Version released!

Download Now!

Here's what's new in Trainer 1149 1.1:

  • Quick Start guide added
  • Welcome screen
  • IEEE 1149.4 basic support
  • Arbitary Boundary Scan instructions support
  • Bug fixes

See also Trainer 1149 1.1 Complete Release Notes.

01.02.2009 - 08:00

Testonica Lab developed and delivered new e-Ticket booking system for one of the largest railway operators in Estonia: Edelaraudtee AS

The new system allows passengers from anywhere in the world buy tickets to the trains online paying via Estonian banks or use a 'self-service" ticket machine at larger stations to buy tickets locally.

The system was designed using the latest Java-based enterprise technologies such as Enterprise beans (EJB 3.0), JPA for persistence layer, Servlets/JSP and Spring framework as a WEB layer stuffing.

The new system is available online at http://www.edel.ee.

Edelaraudtee AS founded in 1997 is mainly known by its diesel trains, which carry passengers mainly to East-South directions in Estonia including Tallinn-Tartu line. The company offers its customers passenger and rail freight carriage services in the domestic transportation market at the best price and quality ratio.

01.07.2008 - 07:00

Testonica Lab signs partnership agreement with ELIKO

Testonica Lab has joined the Competence Center in Electronics, Info and Communication Technologies ELIKO. Participation in ELIKO allowed the company to initiate a new R&D project "Embedded systems test, verification and debug" in cooperation with Tallinn University of Technology and Juku Lab. The main objective of the project is to develop innovative software and hardware solutions in the aforementioned field. The company focuses on development of processor emulation based complex system test solution in connection with Boundary Scan (JTAG) technology. The project is partially funded by Testonica Lab and Juku Lab with major funding coming from the Enterprise Estonia institution.

ELIKO team and its partners have 10+ years practical experiences in development of complex embedded hardware and software systems to be supported by academic advisers from Estonia, Finland, Germany, Italy, Japan, Sweden. The center has an access to the top edge electronic measurement equipment and modern rapid prototyping tools.

Enterprise Estonia promotes business and regional policy in Estonia and is one of the largest institutions of the national support system for entrepreneurship in Estonia, providing financial assistance, advisory, cooperation opportunities and training for the entrepreneurs, research establishments, public and third sector.

24.09.2007 - 07:00

Strategic Alliance between GOEPEL electronic and Testonica Lab

Testonica Lab has entered into an extensive strategic alliance with the German company GOEPEL electronic. GOEPEL electronic is a developer and manufacturer of innovative extended JTAG/Boundary Scan test solutions.

Within the scope of this agreement, Testonica becomes GOEPEL electronic's Centre of Expertise (COE). This includes membership in the "GÖPEL electronic Alliance Partner Network", in which more than 300 specialists are involved to ensure the worldwide customer support of GOEPEL electronic products.

Read complete press release.

25.03.2007 - 14:11

DefSim Personal 1.3.5 version released!

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Here's what's new in DefSim Personal 1.3.5:

  • JRE included into installer package
  • Icons not loaded bug fixed
  • Path is determined correctly when starting not from the default location
  • Several minor bugs fixed

See also DefSim Personal 1.3.5 Complete Release Notes.

For more information, please visit http://defsim.testonica.com

25.12.2006 - 08:00

Trainer 1149 1.0RC3 version released!

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Here's what's new in Trainer 1149 1.0RC3:

  • Several bug fixes

See also Trainer 1149 1.0RC3 Complete Release Notes.

27.11.2006 - 08:00

Trainer 1149 1.0RC2 version released!

Download Now!

Here's what's new in Trainer 1149 1.0RC2:

  • Signals Watcher
  • Comments Editor
  • HTML support for Text Editor

See also Trainer 1149 1.0RC2 Complete Release Notes.

01.11.2006 - 08:00

Trainer 1149 1.0RC1 version released!

Download Now!

Here's what's new in Trainer 1149 1.0RC1:

  • Three working modes separated: Project Mode, Debug Mode (NEW!), Board Edit Mode
  • Hardware support
  • SVF module and Test Composer modules
  • Graphic core accelerated
  • State Diagram View improved
  • Component Details Window
  • Bug fixes

See also Trainer 1149 1.0RC1 Complete Release Notes.

14.06.2006 - 07:00

Trainer 1149 0.8.8 version released!

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Here's what's new in Trainer 1149 0.8.8:

  • New version notifier
  • Several bug fixes

See also Trainer 1149 0.8.8 Complete Release Notes.

26.05.2006 - 07:00

DefSim Portal is available now!

Today we launched a new, dedicated website for our most recent project, DefSim. Everyone's invited - click here and enjoy it!

25.05.2006 - 16:35

DefSim Personal 1.3 version released!

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Here's what's new in DefSim Personal 1.3:

  • Fixed serious bug that lead to crash when working with 2 or more devices simultaneously
  • New version notifier
  • Fine tuning of hardware access module added
  • Small user interface improvements
  • Printing bugs fixed
  • Invalid order of "OK/Fail" marks in single defect mode is fixed

See also DefSim Personal 1.3 Complete Release Notes.

For more information, please visit http://defsim.testonica.com

26.04.2006 - 14:01

DefSim Personal 1.2 version released!

Download Now!

Here's what's new in DefSim Personal 1.2:

  • Installation User Guide included to the release
  • A major bug in displaying fault table for c17 is fixed
  • Order/invalid names of defects for some circuits corrected

See also DefSim Personal 1.2 Complete Release Notes.

For more information, please visit http://defsim.testonica.com

12.04.2006 - 07:00

DefSim Personal 1.1 version released!

Download Now!

Here's what's new in DefSim Personal 1.1:

  • User interface is improved
  • Java version checker added to installer
  • New icons added
  • Minor bugs are fixed

See also DefSim Personal 1.1 Complete Release Notes.

For more information, please visit http://defsim.testonica.com

27.02.2006 - 08:00

DefSim Personal 1.0 Final version released!

Download Now!

Here's what's new in DefSim Personal 1.0 Final:

  • Fault table look & feel greatly improved
  • Code for communication with hardware is completely rewritten to be more realible
  • Printing results capability is added
  • Java version checker added to avoid JVM incompatibilities
  • Icons added
  • Lot of bugs fixed

See also DefSim Personal 1.0 Complete Release Notes.

For more information, please visit http://defsim.testonica.com

15.01.2006 - 16:51
IEEE Computer Society Golden Member award was initiated in 1996 to recognize outstanding contributions from Society members or staff. Current
Computer Society members or long-standing staff are eligible for Golden
Core recognition if they have received one of the Society's top five
service awards like Meritorious or Distinguished Service Certificate or
Outstanding Contribution Certificate. Read more

In 2005, our President, Prof. Raimund Ubar received an IEEE Golden Core Member award after being awarded an IEEE Meritous service Award a year ago.

07.12.2005 - 16:45

Springboard for Testonica Lab organized by Connect Estonia took place in Tallinn. A board of experts was called together to evaluate the future plans of the company. For Testonica Lab, this event turned to be a very important step that helped the company refining its strategy and making several important contacts. Read more about this event in Vincent Oberle's blog.

The Springboard Programme is a process during which the development of growing and start-up companies is considerably enhanced. Such an enhancement is achieved by the involvement of considerable expertise, which is carried by the representatives of the companies belonging to the network. Read more about the Connect Estonia Springboard Programme here.

22.11.2005 - 16:34

Beta version of DefSim Personal software released!
For more information, please visit http://defsim.testonica.com

10.11.2005 - 19:40

DefSim Classroom is available now!
For more information, please visit http://www.defsim.com

28.09.2005 - 16:32

The history was made on 28th of September, 2005 with the notary signing the company statute of Testonica Lab, according to the law of Estonian Republic. The contract was signed by co-founders: Sergei Devadze, Artur Jutman, Vjatseslav Rosin, Vladislav Vislogubov and Raimund-Johannes Ubar. The company will essentially focus on the development of new technologies, tools, and services in the area of digital test and design for test.